Digital Logic Design

In: Computers and Technology

Submitted By amnaf95
Words 492
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12/11/2013

Digital Logic Design CSE-241
Unit 21

4-bit Asynchronous Counter:

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MODULUS OF A COUNTER:
 The modulus of a counter is the number of unique states that

the counter will sequence through. The maximum possible number of states (maximum modulus) of a counter is 2n. Where n is the number of flip-flops in the counter.

TRUNCATED SEQUENCES:
 Counters can also be designed that have a number of states in

their sequence that is less than the maximum of 2n.the resulting sequence is called a truncated sequence.
Muhammad Usman Arif

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ASYNCHRONOUS DECADE COUNTER:
 To obtain a truncated sequence, it is necessary to force the

counter to recycle before going through all of its possible states. For example, the BCD decade counter must recycle back to the 0000 state after the 1001 state. One way to make the counter recycle after the count of nine (1001) is to decode count ten (1010) with a NAND gate and connect the output the clear (CLR) input.

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ASYNCHRONOUS DECADE COUNTER:

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PARTIAL DECODING:
 Notice in the figure that only Q1 and Q3 are connected to

the NAND gate inputs. This arrangement is an example of partial decoding; in which the two unique states (Q1 = 1 and Q3 =1 ) are sufficient to decode the count of ten because none of the other states (zero through nine) have both Q1 and Q3 HIGH at the same time. When the counter goes into count ten (1010), the decoding gate output goes LOW and asynchronously resets the flip-flops.

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SYNCHRONOUS COUNTERS:
 In a synchronous counter, also known as a parallel counter, all

the flip-flops in the counter change state at the same time in synchronism…...

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